I am a PhD student in Computer System Laboratory (CSL) at Cornell University. My research interests are computer architecture, high level synthesis and very large scale integration. I am being advised by Prof. David Albonesi and Prof. Zhiru Zhang. You can find my CV.
PhD in Computer Architecture
BTech in Electrical Engineering, 2014
Indian Institute of Technology, Kanpur
This is an introduction tutorial to gem5 simulation framework
This is an introduction tutorial on gem5 minor cpu model.
Many a times it gets difficult for the computer architects to get started with event-driven simulators. This document is written to target that audience and provide an overview of the minor cpu model in gem5 which implements an in-order pipelined processor. If you have never worked on event-driven simulators and don’t know what they are, there is a cool video here. This tutorial will help the reader to understand how the event-driven minor cpu model is implemented in gem5 and will not go much into details of how to compile and build gem5, how to add tracing and what are ports and how do they work. This information can be found in Learning Gem5. OK!! So lets get started.
This is a tutorial on how to add an instruction to the RISCV ISA, how to write program with the special instruction. I will also talk about how to add the new instruction to RISCV assembler and how to execute it on gem5.
This is a tutorial on how to add statistics in gem5.
This is an introduction tutorial on different types of simulation techniques and a brief overview of event driven simulators.
I have been TA for following courses at Cornell University: